If I buy one of these chips, what happens when Intel give the cache layout back?
Seriously, I would have thought that cache sizes and connectivity were pretty much determined by the speed of the cores, the plumbing joining them to the outside world, and the assumptions about typical workload. I also expect we've seen similar plans in the mainframe and RISC world. To accuse Intel of borrowing AMD's plan is a bit like accusing bats of pinching the idea of wings from the birds, oblivious to the fact that insects got there first.
I'm not saying Nehalem's design isn't newsworthy, but I do question the choice of language.
Register
Borrowed?
If I buy one of these chips, what happens when Intel give the cache layout back?
Seriously, I would have thought that cache sizes and connectivity were pretty much determined by the speed of the cores, the plumbing joining them to the outside world, and the assumptions about typical workload. I also expect we've seen similar plans in the mainframe and RISC world. To accuse Intel of borrowing AMD's plan is a bit like accusing bats of pinching the idea of wings from the birds, oblivious to the fact that insects got there first.
I'm not saying Nehalem's design isn't newsworthy, but I do question the choice of language.